In an information processing apparatus such as an optical disk apparatus, data is generated through parallel data communication executed between the information processing apparatus and a host computer, and various types of information processings (for example, writing and reading processings with respect to the optical disk) are executed to the obtained data.
In the information processing apparatus, a program for executing the parallel data communication between the information processing apparatus and the host computer (hereinafter, referred to as communication program), and the like, are stored in a ROM memory. A program in charge of the whole apparatus which executes a control operation and the like to the communication program stored in the ROM memory, and the like, (hereinafter, referred to as whole program, and generally called firmware (hereinafter F/W)) are stored in a non-volatile memory (Flash ROM or the like). In normal operations, the whole program written in the non-volatile memory is executed on the non-volatile memory so that the various types of processings are executed. At the time, data generated in the information processings including the data generated in the parallel data communication between the information processing apparatus and the host computer is temporarily recorded in a volatile memory (cash memory: SDRAM or the like).
The information processing apparatus such as the optical disk apparatus is increasingly advanced in order to respond to new media such as a recording DVD (Digital Versatile Disk) and BD (Blue-ray Disk), as a result of which a whole system is inevitably increasing in its scale. Accordingly, a processing power of a CPU which controls the whole system is inadequate in some cases, possible solutions for which are to increase a speed of the CPU, realize a parallel processing using a plurality of CPUs, and the like. In fact, there exist some information processing apparatuses in which one CPU conventionally controlled the whole system, such as the optical disk apparatus, the whole system is controlled in such a manner that a processing load is divided by the plurality of CPUs in order to respond to more advanced functions in terms of costs and power consumption.
When the information processing apparatus is being manufactured or repaired, the whole program is written in the non-volatile memory of the information processing apparatus from the host-computer side. At the time, in the information processing apparatus, the whole program has not been stored (when manufactured), or an operation of the whole program is incomplete though already stored (when repaired).
As another solution, an information processing apparatus comprising a storage state judging unit for judging whether or not the whole program is stored in the non-volatile memory was invented. In the information processing apparatus, a code for judging whether or not the whole program is stored in the non-volatile memory (for example, check sum code, or the like) is embedded in the whole program of the non-volatile memory so that the storage state judging unit can thereby judge the storage state.
Examples of the conventional information processing apparatus are recited in No. 2001-075796, No. 2000-105694, No. 2000-010666, No. 2002-157137, and No. 2001-243122 of the Publication of the Unexamined Japanese Patent Applications.
As described earlier, when the information processing apparatus is being manufactured or repaired, the whole program has not been stored in the information processing apparatus (when manufactured), or the operation of the whole program is incomplete though already stored (when repaired). In order to deal with the situations in the conventional system in which one CPU is used (hereinafter, referred to as 1-CPU system), there were made available an apparatus configuration and a method wherein the whole program could be transmitted to the information processing apparatus from the host computer through the parallel data communication and easily written in the non-volatile memory in the case where program execution starts in the ROM memory.
In the case of the system in which the plurality of CPUs are used (hereinafter, referred to as plurality-CPU system), however, activation steps and operational states of the respective CPUs affect the operation of the other CPU. Therefore, the following four different problems are generated in terms of the activation step and the operational states of the CPUs in a system (hereinafter, referred to as 2-CPU system) where the CPU comprising the ROM memory (hereafter, referred to as first CPU) and the CPU comprising the non-volatile memory (hereinafter, referred to as second CPU) are used.
The Second CPU is First Activated
When the non-volatile memory is being manufactured or repaired, the second CPU runs away. Then, the whole system is non-operable, which makes it impossible to execute any processing.
The First CPU is First Activated
Because the first CPU is unable to access the non-volatile memory, it becomes impossible to write the whole program in the non-volatile memory, confirm a state where the whole program is being written in the non-volatile memory, and the like.
The First and Second CPUs are Simultaneously Activated
In the case where the second CPU affects the operation of the first CPU, the second CPU runs away, thereby affecting the operation of the first CPU, which makes it impossible to guarantee the operation of the system.
Even in the case where the second CPU does not affect the operation of the first CPU, the first CPU is normally operated, however, unable to grasp the operational state of the second CPU, which also makes it impossible to guarantee the operation of the system.
Neither of the Program of the First CPU Nor the Program of the Second CPU Has Not Been Stored or the Operations of the Programs are Incomplete Though Already Stored
When the ROM memory of the first CPU is replaced with a RAM memory during a development process, in particular, the CPU inevitably runs away, which breaks down the system.
Due to the problems described above, an apparatus configuration and a method capable of solving the problems and allowing the whole program to be easily written in the non-volatile memory is desirable also in the plurality-CPU system.
In an optical disk apparatus (information processing apparatus) shown in FIG. 2A as an example of the conventional 1-CPU system, a program (microcode) of a ROM memory (IROM) and a whole program (F/W) of a non-volatile memory (Flash ROM) are processed in a time-sharing manner, which makes it unnecessary for one of the programs to watch an operation of the other program. However, in an optical disk apparatus (information processing apparatus) of the 2-CPU system shown in FIG. 2A according to the present invention, a program (microcode) of a ROM memory (IROM) and a whole program (F/W) of a non-volatile memory (Flash ROM) are independently processed in parallel by two CPUs, which makes it necessary for one of the programs to watch the operation of the other program.
Further, in the case of the method for judging whether or not the whole program is stored in the non-volatile memory using the storage stage judging unit by embedding the code for judging the storage state of the whole program of the non-volatile memory (for example, check sum code, or the like) in the whole program of the non-volatile memory in the information processing apparatus comprising the storage state judging unit for judging the storage state, the code for judging the storage state is embedded at a fixed position in the whole program.
However, when it is undesirable to store the code for judging the storage state at any fixed position in terms of the configuration of the whole program, such a convenience that the whole program has to be reconfigured or some restrictions are imposed on the reconfiguration of the whole program was generated.
Based on the described circumstances, it is desirable to invent such a method that makes it unnecessary to store the code for judging the storage state at any fixed position.